forked from 1b-agent/opencadstudio-upstream
fix(polyline): render fill mode boundaries
Use kernel-produced band outlines when FILLMODE is off. Preserve centerline linetype stations through inserts, clipping, projection, and PDF export.
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@@ -406,40 +406,45 @@ fn pack_color(color: [f32; 4]) -> [u8; 4] {
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/// non-dash-first patterns keep the legacy centred phase.
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fn wire_distances(wire: &WireModel) -> (Vec<f32>, f32, f32) {
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let n = wire.points.len();
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let mut dists = vec![0.0_f32; n];
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let mut has_break = false;
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// Accumulate arc-length in f64 from double-single deltas (high + low). An
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// f32-high-only delta `q[0] - p[0]` quantises ~0.1 at UTM coordinates
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// (−1.2M), which shifts the dash phase and drifts parallel lines out of sync
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// — the reason MLINE elements were CPU-dashed. `points_low` may be empty for
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// non-RTE wires → treat the low half as zero (same as the old behaviour).
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let mut acc = 0.0_f64;
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for i in 1..n {
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let p = wire.points[i - 1];
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let q = wire.points[i];
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if !p[0].is_finite() || !q[0].is_finite() {
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has_break = true;
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// plinegen=false: reset to 0 at the first real point after a NaN separator.
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if !wire.plinegen && !p[0].is_finite() && q[0].is_finite() {
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acc = 0.0;
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let explicit = wire.pattern_stations.len() >= n + 1;
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let (mut dists, has_break, total) = if explicit {
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(
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wire.pattern_stations[..n].to_vec(),
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!wire.plinegen,
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wire.pattern_stations[n],
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)
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} else {
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let mut dists = vec![0.0_f32; n];
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let mut has_break = false;
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// Accumulate arc-length in f64 from double-single deltas (high + low).
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let mut acc = 0.0_f64;
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for i in 1..n {
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let p = wire.points[i - 1];
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let q = wire.points[i];
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if !p[0].is_finite() || !q[0].is_finite() {
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has_break = true;
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if !wire.plinegen && !p[0].is_finite() && q[0].is_finite() {
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acc = 0.0;
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}
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dists[i] = acc as f32;
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} else {
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let pl = wire.points_low.get(i - 1).copied().unwrap_or([0.0; 3]);
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let ql = wire.points_low.get(i).copied().unwrap_or([0.0; 3]);
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let dx = (q[0] as f64 - p[0] as f64) + (ql[0] as f64 - pl[0] as f64);
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let dy = (q[1] as f64 - p[1] as f64) + (ql[1] as f64 - pl[1] as f64);
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let dz = (q[2] as f64 - p[2] as f64) + (ql[2] as f64 - pl[2] as f64);
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acc += (dx * dx + dy * dy + dz * dz).sqrt();
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dists[i] = acc as f32;
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}
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dists[i] = acc as f32;
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} else {
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let pl = wire.points_low.get(i - 1).copied().unwrap_or([0.0; 3]);
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let ql = wire.points_low.get(i).copied().unwrap_or([0.0; 3]);
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let dx = (q[0] as f64 - p[0] as f64) + (ql[0] as f64 - pl[0] as f64);
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let dy = (q[1] as f64 - p[1] as f64) + (ql[1] as f64 - pl[1] as f64);
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let dz = (q[2] as f64 - p[2] as f64) + (ql[2] as f64 - pl[2] as f64);
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acc += (dx * dx + dy * dy + dz * dz).sqrt();
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dists[i] = acc as f32;
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}
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}
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let total = dists.last().copied().unwrap_or(0.0);
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(dists, has_break, total)
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};
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let pat_len = wire.pattern_length;
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if pat_len <= 1e-6 || has_break || n < 2 {
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return (dists, 0.0, 0.0);
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}
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let total = dists[n - 1];
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if total <= 1e-6 {
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return (dists, 0.0, 0.0);
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}
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