refactor(viewport): unify content-viewport clipping on the stencil path

Rectangular paper viewports now go through the same GPU stencil clip as
non-rectangular ones: viewport_clip_boundary_ndc returns the four rect
corners (a full-target mask) instead of nothing, so the render path has
no rect/non-rect special case — every content viewport carries a clip
boundary and draws with stencil reference 0xFF.

With a single clip path, the old per-wire / -image / -wipeout scissor
mechanism is fully dead and removed: compute_*_scissors, the
*_pixel_scissors buffers, the project_scissor helper, the per-pass
set_scissor_rect blocks, the vp_scissor field threaded through
WireModel / ImageModel / HatchModel and their GPU mirrors (WireGpu /
ImageGpu / WipeoutGpu / HatchWebGpu), from_run's scissor parameter, the
scissor grouping in build_wire_buffers, and the is_arena_eligible gate.
Net -245 lines across 54 files.

Rectangular viewports still clip exactly via their own render rectangle;
the stencil mask is a redundant full-target no-op there, kept only so
the clip code path stays uniform. XCLIP keeps its CPU wire clip.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

src/scene/pipeline/wire_gpu.rs

@@ -208,9 +208,6 @@ impl WireInstance {
 pub struct WireGpu {
     pub instance_buffer: wgpu::Buffer,
     pub instance_count: u32,
-    /// Paper-space bbox [x0, y0, x1, y1] for GPU scissor clipping.
-    /// Set only for viewport-projected wires; None for regular wires.
-    pub vp_scissor: Option<[f32; 4]>,
     /// `true` when the source `WireModel` also carries `fill_tris`
     /// (i.e. it is a 3D mesh face — PolyfaceMesh / PolygonMesh — whose
     /// outline lives in `points`). The wire pass skips these instances
@@ -521,7 +518,6 @@ impl WireGpu {
         device: &wgpu::Device,
         wires: &[WireModel],
         depth_map: &rustc_hash::FxHashMap<u64, f32>,
-        scissor: Option<[f32; 4]>,
         mesh_edge: bool,
         const_bgl: Option<&wgpu::BindGroupLayout>,
     ) -> Vec<Self> {
@@ -562,7 +558,6 @@ impl WireGpu {
                     Self {
                         instance_buffer: buf,
                         instance_count: chunk.len() as u32,
-                        vp_scissor: scissor,
                         is_3d_mesh_edge: mesh_edge,
                         const_bind_group: bg.clone(),
                     }
@@ -594,7 +589,6 @@ impl WireGpu {
                     Self {
                         instance_buffer: buf,
                         instance_count: chunk.len() as u32,
-                        vp_scissor: scissor,
                         is_3d_mesh_edge: mesh_edge,
                         const_bind_group: None,
                     }
@@ -652,7 +646,6 @@ impl WireGpu {
                     Self {
                         instance_buffer,
                         instance_count: chunk.len() as u32,
-                        vp_scissor: None,
                         is_3d_mesh_edge: false,
                         const_bind_group: bg.clone(),
                     }
@@ -678,7 +671,6 @@ impl WireGpu {
                     Self {
                         instance_buffer,
                         instance_count: chunk.len() as u32,
-                        vp_scissor: None,
                         is_3d_mesh_edge: false,
                         const_bind_group: None,
                     }