fix(xref): blocks respect their internal draw order

Xref merge now inserts entities in the source block's chain order and
carries SortEntitiesTable objects across (remapped to merged handles).
draw_depth_map values become [depth, half] so exploded block/xref fills
and wide-polyline band wires both compose child depth as
insert_depth + in-block rank x half, recursing into nested inserts with
the same divisor - bands and fills from one block interleave by the
block's internal order instead of stacking at the insert's single depth.
Band batches split per rank via WireModel.depth_override; thin wires
stay merged. The wire arena falls back to a full rebuild when a slab
carries mixed depths so refreshes don't flatten band overrides.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>

src/scene/pipeline/wire_gpu.rs

@@ -488,17 +488,23 @@ pub(crate) fn emit_wire_native(
 
 /// Looks up a wire's draw-order depth from the per-entity map using the
 /// handle encoded in its `name`. Falls back to 0.0 (transient / preview
-/// wires that carry no document handle).
+/// wires that carry no document handle). A wire carrying a block-local
+/// `depth_override` (a wide-polyline band inside a block) composes it into
+/// the insert's own sub-range so the band orders against its block siblings.
 pub(crate) fn wire_draw_depth(
     wire: &WireModel,
-    depth_map: &rustc_hash::FxHashMap<u64, f32>,
+    depth_map: &rustc_hash::FxHashMap<u64, [f32; 2]>,
 ) -> f32 {
-    wire
+    let base = wire
         .name
         .parse::<u64>()
         .ok()
-        .and_then(|h| depth_map.get(&h).copied())
-        .unwrap_or(0.0)
+        .and_then(|h| depth_map.get(&h).copied());
+    match (base, wire.depth_override) {
+        (Some([d, half]), Some(local)) => d + local * half,
+        (Some([d, _]), None) => d,
+        (None, _) => 0.0,
+    }
 }
 
 /// Build the shared per-wire `WireConst` storage buffer and its bind group
@@ -546,7 +552,7 @@ impl WireGpu {
     pub fn from_run(
         device: &wgpu::Device,
         wires: &[WireModel],
-        depth_map: &rustc_hash::FxHashMap<u64, f32>,
+        depth_map: &rustc_hash::FxHashMap<u64, [f32; 2]>,
         mesh_edge: bool,
         const_bgl: Option<&wgpu::BindGroupLayout>,
     ) -> Vec<Self> {
@@ -632,7 +638,7 @@ impl WireGpu {
     pub fn from_batch(
         device: &wgpu::Device,
         wires: &[WireModel],
-        depth_map: &rustc_hash::FxHashMap<u64, f32>,
+        depth_map: &rustc_hash::FxHashMap<u64, [f32; 2]>,
         const_bgl: Option<&wgpu::BindGroupLayout>,
     ) -> Vec<Self> {
         let total_segs: usize = wires.iter().map(|w| w.points.len().saturating_sub(1)).sum();