forked from 1b-agent/opencadstudio-upstream
HakanandClaude Opus 4.7
d3986e9cba
Documents the 4-step plan to reduce first-file-open latency by attacking wire vertex upload volume: mapped_at_creation, Rayon parallel emit, instanced rendering (the big lever, ~6.5x memory cut), and per-instance packing. Each step lands as its own commit. Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
81 lines
3.5 KiB
Markdown
81 lines
3.5 KiB
Markdown
# Wire Pipeline — Cold-Open Optimization Plan
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Goal: reduce first-file-open latency (tessellate → upload → GPU buffer
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creation) for wire entities. Steady-state draw cost is already cheap; the
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bottleneck on cold open is **upload volume** and **vertex emission**.
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## Baseline
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Each wire segment currently produces **6 vertices × 96 B = 576 B**. The same
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`pos_a / pos_b / color / half_width / pattern_length / pat0 / pat1` values
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are duplicated across all 6 corners of the quad. For a drawing with 1 M
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segments this is **~576 MB** of CPU-side `Vec<WireVertex>` plus the same
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amount uploaded over PCIe.
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Build path: `WireGpu::from_batch` (single-threaded loop) → `Vec<WireVertex>`
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→ `create_buffer_init` (one alloc + one memcpy into a staging buffer the
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driver then DMAs to VRAM).
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## Step 1 — `mapped_at_creation` upload
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Replace `create_buffer_init(contents)` with `create_buffer(mapped: true)` +
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write the vertex stream directly into the mapped slice. Skips the
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intermediate `Vec<WireVertex>` → staging-buffer memcpy.
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- **Files**: `src/scene/pipeline/wire_gpu.rs`
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- **Risk**: low (size known ahead of time; no semantic change).
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- **Expected win**: 1 alloc + 1 memcpy per buffer dropped. Modest but free.
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## Step 2 — Rayon parallel vertex emission
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`from_batch` walks wires serially. Each wire's vertex generation is
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independent (no shared state, no order dependency — wires are already
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keyed by style upstream in `block_cache`). Use `rayon::par_iter().flat_map`
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to emit per-wire vertex slices in parallel, then concatenate.
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- **Files**: `src/scene/pipeline/wire_gpu.rs`
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- **Risk**: low. Output ordering does not matter for correctness.
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- **Expected win**: N-core speedup on multi-wire drawings; meaningful on
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files with many short wires (typical CAD geometry).
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## Step 3 — Instanced rendering (the big win)
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Replace 6-vertex quad expansion with **1 instance per segment** + 4-vertex
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unit quad shared across all instances. Per-instance struct (~88 B) holds:
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`pos_a, pos_b, color, distance_a, distance_b, half_width, pattern_length,
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pat0, pat1`. `which_end` and `side` are derived from `@builtin(vertex_index)`
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inside the vertex shader.
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- **Files**: `src/scene/pipeline/wire_gpu.rs`, `src/shaders/wire.wgsl`,
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`src/scene/pipeline/mod.rs` (pipeline `VertexBufferLayout`).
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- **Risk**: medium. Two vertex buffers (per-vertex + per-instance), shader
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derives `which_end` / `side` from `vertex_index`. `WireGpu::from_batch`
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emits 1 instance per segment instead of 6 verts.
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- **Expected win**: **~6.5× less GPU memory & upload bandwidth per
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segment** (576 B → 88 B). Biggest cold-open lever.
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## Step 4 — Tighter per-instance packing
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After Step 3 the instance struct is the new hot path. Pack:
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- `color: [f32; 4]` → `[u8; 4]` (`Unorm8x4`): 16 B → 4 B, no visible
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quality loss at 8-bit display.
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- `which_end / side` already eliminated by Step 3.
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- `pat0 / pat1` stay (encoder relies on up to 8 dash elements).
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Net: ~88 B → ~76 B per instance. ~15 % further reduction on top of Step 3.
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- **Files**: `src/scene/pipeline/wire_gpu.rs`, `src/shaders/wire.wgsl`.
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- **Risk**: low (vertex-attribute format change only).
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- **Expected win**: ~15 % less upload after Step 3.
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## Ordering rationale
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1-2 first — independent, low risk, immediate wins.
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3 next — restructures the pipeline; depends on no prior changes but is the
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single biggest lever.
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4 last — only pays off after Step 3 turns the per-instance struct into the
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hot path.
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Each step ends with a `cargo check` (warnings-free) and a commit.
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